Reducing power consumption in memory devices is becoming more important, particularly in view of their growing use in mobile applications and devices, including, for example, cell phones, handheld computing devices (e.g., Blackberry® devices, a registered trademark of Research in Motion Limited), MP3 players (e.g., iPod®, a registered trademark of Apple Inc.), global positioning system (GPS) instruments, laptop and palmtop computers, etc. Leakage current in memory devices contributes significantly to standby power consumption in the memory devices. For instance, in a memory array (e.g., read only memory (ROM)) which includes a plurality of column lines and row lines, with associated row line drivers, for selectively reading one or more memory cells in the memory array, the row line drivers are responsible for a large portion of the overall leakage current due, at least in part, to the large number of driver circuits employed therein.
Memory arrays typically include row decode circuitry employing a decoder and a row line driver for driving a given row line to a logic high (e.g., “1”) or a logic low (e.g., “0”) voltage level in order to selectively enable read access devices associated with a corresponding row of memory cells connected to the given row line. Each row of memory cells in the memory array requires a separate row line driver to drive the access devices of the memory cells in that row. For even moderate size memory arrays, the load presented by a row line can be quite large, thereby requiring large drivers in order to achieve reasonable memory access times. Unfortunately, leakage current in the driver generally increases with the size of the driver. Moreover, as semiconductor device geometries shrink, leakage current in these devices increases, thereby exacerbating the problem. Accordingly, it is desirable to reduce leakage current in a memory row line driver circuit.
One conventional approach to reducing leakage current in a ROM is to utilize series pull-up or pull-down transistors in output stages of row line drivers in the ROM. This approach, however, results in slower memory performance due primarily to increasing rise and/or fall times of the row lines. Another approach is to employ an output stage in the row line driver having a pair of stacked p-channel metal-oxide-semiconductor (PMOS) devices connected to each row line at an intermediate node between the two devices. Specifically, a source of a first PMOS device is connected to a voltage supply of the row line driver, a drain of the first device is connected to a source of a second PMOS device at the intermediate node, a drain of the second device is connected to a voltage return of the circuit, and gates of the two devices are connected to one or more control signals. The methodology of using stacked PMOS devices, however, relies on sub-threshold leakage current to lower a voltage at the intermediate node of the PMOS stack. As a result, it takes a significant amount of time for the intermediate node to equalize to a low-current state following a row line access, which is undesirable.
Accordingly, there exists a need for techniques for reducing leakage current in a memory device which do not suffer from one or more of the above-described problems associated with conventional memory devices.